1. Field of the Invention
The present invention generally relates to arithmetic units for digital computers and, more particularly, to a carry select adder that includes zero and one detection circuitry.
2. Background Description
In a microprocessor, it is often necessary to check for overflow or underflow on the result of some operation. A separate zero and one detection function unit is conventionally performed on the output of an adder.
A zero detection unit operates in the binary system to check an output to determine if the output is all zeros (i.e., 0000). The one detection unit similarly checks if the output is all ones (i.e., 1111).
The zero detect function is necessary in units that compare two inputs to determine if they are equal and in floating point operations to determine underflow or overflow.
The conventional method of zero/one detection is to perform the addition in one unit and then check if the output bits are all ones or all zeros in a separate unit. This check is conventionally done in series with the addition operation. In some existing processor designs, the zero and one detection is done in a tree fashion, checking for all zeros or all ones in 4-bit slices. The 4-bit results are then combined into intermediate signals for 8, 16, 32 or 64-bit results. The timing of the zero and one detection is critical to the operational speed of the processor.